The present invention relates to circuits for translating between transistor-transistor logic (TTL) and emitter-coupled logic (ECL).
TTL circuits typically operate between 0 and 5 volts, with the low voltage level being between 0 and 0.8 volts and the high voltage level being between 2.0 and 5.0 volts. ECL circuits, on the other hand, typically operate with a -4.5 volt supply and define a high logic level between -0.880 volts and -1.165 volts and a low logic level between -1.475 volts and -1.810 volts. The purpose of a translator circuit is to transform high and low logic levels from the TTL circuit to high and low logic levels, respectively, to be supplied to an ECL circuit.
An example of a prior art translator circuit is shown in FIG. 1. A TTL input 10 is coupled through a diode 12 to the base of a transistor 14. The emitter of transistor 14 is coupled through a resistor 16, a pair of diodes 18, 20 and a resistor 22 to an ECL output 24. The collector of transistor 14 is coupled to a positive TTL voltage supply 26. ECL output 24 is coupled through a transistor 28 and a resistor 30 to a negative ECL voltage supply 32. The base of transistor 28 is coupled to a voltage equal to the current source voltage of the ECL circuit plus a voltage equal to the base-emitter voltage drop (.phi.) of a transistor. Four diodes 34, 36, 38 and 40 couple the base of transistor 14 to ground. A diode 42 couples resistor 16 to ground. A resistor 44 couples the base of transistor 14 to the positive voltage supply 26.
The circuit of FIG. 1 operates as follows. A constant current flow from the positive voltage supply 26 to negative voltage supply 32 is provided through transistor 14, resistor 16, diodes 18 and 20, resistor 22, transistor 28 and resistor 30. These elements, through the voltage drop caused by this current, generate the voltage shift needed to translate from TTL to ECL. The value of the current is constant and is giving by the voltage potential across R30 divided by the value of R30. The voltage at one end of R30 is V.sub.EE, while the voltage at the other end is the base voltage of transistor 28 (V.sub.CS +.phi.) less the base-emitter voltage of transistor 28 (.phi.). The current is thus given by the following equation: ##EQU1##
FIG. 2 shows a plot of the voltage at various nodes in the circuit of FIG. 1 vs. the voltage at TTL input 10. The voltage at node 46 increases from .phi. (the base-emitter voltage drop, approximately 0.8 volts) due to the voltage drop across diode 12 to a maximum value of 4.phi., which is the high level clamp by diodes 34-40. Node 48 at the emitter of transistor 14 follows a similar path at a level of .phi. below node 46. Node 50 follows node 48 until diode 42 clamps node 50 at a voltage of .phi.. Finally, nodes 52 and 54 follow the voltage at node 50 as shown. Diode 42 thus limits the high level ECL output and diodes 34-40 correspondingly limit the voltage at the base of transistor 14 so that current is not wasted for the clamped high level ECL output. As can be seen from FIG. 2, the slope of the output transfer curve for node 54 is less than one, meaning that the circuit has attenuation since the voltage gain is less than one. The wide transition region makes the circuit susceptible to noise.